The operating performance of a data processing system can depend on the rate at which information can be stored and retrieved at a memory device. Many types of memory, such as double data rate (DDR) dynamic random access memory (DRAM), operate at higher levels of access efficiency when memory accesses are scheduled, or reordered, so that the same local region of a memory is consecutively accessed. While single-core processors or single-thread applications frequently can exhibit this locality, the implementation of multiple processor cores or multi-threaded applications typically results in an interleaving of memory access requests to disparate locations in the memory. As a result, multi-core processors and multi-threaded applications can render conventional memory access scheduling techniques ineffective.